![]() Innovative and creative, you proactively explore new ideas and adapt quickly to change.Īn investment in your future, is an investment in ours.You're collaborative, building relationships, humbly offering support and openly welcoming approaches. ![]() An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.You're inclusive, adapting your style to the situation and diverse global norms of our people.Experience and knowledge of assembly process, test, and characterization techniques would be an added advantage.Experience in Cadence Allegro platform tools (PCB Editor, Advanced Package Designer, APD/SiP, Concept HDL, Sigrity), and/or Mentor Xpedition platform tools (PCB Layout/XPD, Designer, Hyperlynx).Experience with design and electromagnetic simulation tools: Mentor, Cadence tools, SPICE, Ansys tools, etc.Understand the interaction of Silico Chip + Package and Board.Understand packaging technology development FMEAs and product packaging requirements - both physical and electrical.Strong technical background in design and electrical analysis.Bachelors Degree in Electrical Engineering or related Physical Science with 15+ years of experience or Masters in Electrical Engineering or related Physical Science with 13+ Years of Industry Experience or PhD in Electrical Engineering or related Physical Science with 10+ yrs of Industry Experience Preferred.Complete other responsibilities as assigned.Establish and maintain package design rule.Participate in packaging roadmap development and focus on execution.Design and develop a package and interconnect methods in the areas of SiP/modules, wafer level, flip-chip, and multi-chip module.Performs custom physical design and design flow development, APR tools, and multi-chip design validation.Work with the Si and Board design teams to define and implement a co-design strategy that would optimize product performance and cost at the package and system level.Responsible for package design and design flow development for advanced packaging technologies in a cross-functional team.Responsible for the advanced packaging CAD flow set-up, CAD tool bring-up, and related areas.Responsible for the thermal/mechanical/electrical design, analysis, and development of electronic packages.Location : Onsite at our San Jose headquarters 5 days a week with an average of 10% travel per year Mission of the Packaging Solutions Center is to find package solutions beyond Silicon to make next performance systems considering power and cost and to tackle the difficult and hugely innovative task with the industry, focusing on Advanced Packages such as 2.5D, 3D, and 3.5D.Īs an IC Packaging Design Engineer, you will participate in Samsung's High-end Advanced Packages, mainly, Design and Electrical Analysis (SI/PI) for high bandwidth and low power Advanced Packaging (ex: SiP, 2.5D, 3D, 3.5D, etc.). Semiconductor IC Packaging Design Engineer will provide conventional and/or advanced package design/development and sustaining support for integrated circuit or semiconductor assemblies, various other electronic components, and/or completed units. ![]() Together, we're building a better tomorrow for our employees, customers, partners, and communities. We're dedicated to empowering people to be their true selves. We believe that innovation and growth are driven by an inclusive culture and a diverse workforce. ![]() Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. Our technology solutions power the tools you use every day-including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Advancing the World's Technology Together
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